Bae Hagyoul, Park Tae Joon, Noh Jinhyun, Chung Wonil, Si Mengwei, Ramanathan Shriram, Ye Peide D
Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, United States of America.
Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907, United States of America.
Nanotechnology. 2021 Dec 24;33(12). doi: 10.1088/1361-6528/ac3f11.
Nano-membrane tri-gate-gallium oxide (-GaO) field-effect transistors (FETs) on SiO/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between-GaOand gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (AlO) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope () of 61 mV dec, high drain current () ON/OFF ratio of 1.5 × 10, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current-voltage (-) characteristics measured at temperatures up to 400 °C.
首次展示了通过剥离工艺在SiO/Si衬底上制备的纳米膜三栅氧化镓(-GaO)场效应晶体管(FET)。通过采用电子束光刻技术,可以定义最小尺寸特征,其足迹沟道宽度为50nm。为了在-GaO和栅极电介质之间形成高质量界面,使用原子层沉积的15nm厚氧化铝(AlO)并进行三甲基铝(TMA)自清洁表面处理。所制备的器件表现出极低的亚阈值斜率()为61mV/dec,高漏极电流()开/关比为1.5×10,以及可忽略不计的转移特性滞后。我们还通过在高达400°C的温度下测量电流-电压(-)特性,实验证明了这些器件的稳健性。