Enhancement-Mode Ambipolar Thin-Film Transistors and CMOS Logic Circuits using Bilayer GaO/NiO Semiconductors.

Recent advancements in power electronics have been driven by GaO-based ultrawide bandgap (UWBG) semiconductor devices, enabling efficient high-current switching. However, integrating GaO power devices with essential silicon CMOS logic circuits for advanced control poses fabrication challenges. Researchers have introduced GaO-based NMOS and pseudo-CMOS circuits for integration, but these circuits may either consume more power or increase the design complexity. Hence, this article proposes GaO-based CMOS realized using heterogeneous 3D-stacked bilayer ambipolar transistors. These ambipolar transistors consist of HfO/NiO/GaO/NiO/HfO heterostructures that are wrapped around by the Ti/Au gate electrode, resulting in record high electron and hole current on/off ratios of 10 and 10. The threshold voltage, subthreshold swing, and current density measured from 100 ambipolar devices (across 5 batches) are around -7.99 ± 0.92 V (p-channel) and 7.81 ± 0.81 V (n-channel), 0.59 ± 0.07 V/dec (p-channel) and 0.61 ± 0.06 V/dec (n-channel), and 0.99 ± 0.26 mA/mm (p-channel) and 58.23 ± 12.99 mA/mm (n-channel), respectively. All the 100 ambipolar devices showed decent long-term stability over a period of 200 days, exhibiting reliable electrical performance. The threshold voltage shift (Δ) after negative bias stressing for a period of 3500 s is around 11.52 V (p-channel) and 10.21 V (n-channel), respectively. Notably, the n-channels exhibit ∼2 orders higher on/off ratio than the best GaO unipolar transistors at 300 °C. Moreover, the polarities of ambipolar transistors are reconfigurable into p- or n-MOS, which are integrated to demonstrate CMOS inverter, NOR, and NAND logic gates. The switching periods from "0" to "1" and from "1" to "0" of NOR are 0.12 and 0.17 μs, and those of NAND are 0.16 and 0.13 μs. This work lays the foundation of oxide-semiconductor-based CMOS for future integrated electronics.